1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display device and a driving method thereof that are adapted to display a certain information to a user when no signal is input after a power was applied to the liquid crystal display device.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) has been employed a notebook PC, an office automation equipment and an audio/video equipment, etc. owing to advantages of a small dimension, a thin thickness and a low power consumption. In particular, an active matrix liquid crystal display using thin film transistors (TFT's) as switching devices is suitable for displaying a dynamic image.
FIG. 1 is a block diagram showing a configuration of the conventional LCD. In FIG. 1, an interface part 10 receives a data (RGB data) and control signals (e.g., an input clock, a horizontal synchronizing signal, a vertical synchronizing signal and a data enable signal) inputted from a driving system such as a personal computer (not shown) to apply them to a timing controller 12. A low voltage differential signal (LVDS) interface and a transistor transistor logic (TTL) interface are largely used for a data and control signal transmission to the driving system. Such interfaces may be integrated into a single chip along with the timing controller 12 by collecting each function of them.
The timing controller 12 takes advantages of a control signal inputted via the interface 10 to produce control signals for driving a data driver 18 consisting of a plurality of drive IC's (not shown) and a gate driver 20 consisting of a plurality of gate drive IC's (not shown). Also, the timing controller 12 transfers a data inputted from the interface 10 to the data driver 18. A reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the data driver 18, which are established by a producer on a basis of a transmissivity to voltage characteristic of the panel. The data driver 18 selects reference voltages of an input data in response to control signals from the timing controller 12 and applies the selected reference voltage to the liquid crystal display panel 2, thereby controlling a rotation angle of the liquid crystal. The gate driver 20 makes an on/off control of the thin film transistors (TFT's) arranged on the liquid crystal panel 22 in response to the control signals inputted from the timing controller 12. Also, the gate driver 20 allows the analog image signals from the data driver 18 to be applied to each pixel connected to each TFT. A power voltage generator 14 supplies an operation voltage to each element, and generates a common electrode voltage and applies it to the liquid crystal panel 22.
FIG. 2 is a schematic block diagram showing a configuration of the timing controller in FIG. 1. In FIG. 2, the timing controller 12 includes a control signal generator 22 and a data signal generator 24. The timing controller 12 receives a horizontal synchronizing signal, a vertical synchronizing signal, a data enable signal, a clock and a data (R,G,B). The vertical synchronizing signal represents a time required for displaying one frame field. The horizontal synchronizing signal represents a time required for displaying one line of the field. Thus, the horizontal synchronizing signal includes pulses corresponding to the number of pixels included in one line. The data enable signal represents a time supplying the pixel with a data.
The data signal generator 24 rearranges a data so that desired bits of data (R,G,B) inputted from the interface 10 can be supplied to the data driver 18. The control signal generator 22 receives the horizontal synchronizing signal, the vertical synchronizing signal, the data enable signal and the clock signal to generate various control signals and apply them to the data driver 18 and the gate driver 20. The control signals required for the data driver 18 and the gate driver 20 will be described below. Herein, the control signals used commonly other than the control signals required specially will be described.
The control signals required for the data driver 18 include source sampling clock (SSC), source output enable (SOE), source start pulse (SSP) and liquid crystal polarity reverse (POL) signals, etc. The SSC signal is used as a sampling clock for latching a data in the data driver 18, and which determines a drive frequency of the data drive IC. The SOE signal transfer a data latched by the SSC signal to the liquid crystal panel. The SSP signal is a signal notifying a latch or sampling initiation of the data during one horizontal synchronous period. The POL signal is a signal notifying the positive or negative polarity of the liquid crystal for the purpose of making an inversion driving of the liquid crystal.
The control signals required for the gate driver 20 include gate shift clock (GSC), gate output enable (GOE) and gate start pulse (GSP) signals, etc. The GSC signal is a signal determining a time when a gate of the TFT is turned on or off. The GOE signal is a signal controlling an output of the gate driver 20. The GSP signal is a signal notifying a first drive line of the field in one vertical synchronizing signal.
The control signals inputted to the data driver 18 and the gate driver 20 as mentioned above are generated by the control signals inputted from the interface 10. Thus, if no control signal is input from the interface 10, then the timing controller 12 fails to generate a control signal. In other words, if any control signals are not inputted from the interface 10 in a power-on state, then the liquid crystal panel 2 does not display a picture. If a state in which the liquid crystal panel 2 does not display a picture upon power-on is sustained, then the liquid crystal is deteriorated to leave traces. Such deteriorated traces is viewed even when the LCD make a normal display to cause a trouble of the LCD.